1. Field of the Invention
The present invention relates to a power supply including amplifier means for amplifying a reference voltage and for outputting the amplified voltage and particularly to a stabilized voltage supply usable with multi-source IC and the like.
2. Description of the Related Art
CD players require a high-accuracy servo control for the pickup. For example, the tracking servo control or pickup focus servo circuit must have a particularly high accuracy in control. A power supply for supplying a power voltage to such high-accuracy servo control circuits (but not limited to those of the CD players) is required to have extremely small fluctuations in the output voltage. Therefore, such a type of power supply should be formed so as to provide a stabilized output voltage, that is, a so-called stabilized voltage supply.
FIG. 5 shows the principle of such a power supply. A circuit generally shown by 6 in FIG. 5 comprises a differential amplifier 2 and an output transistor 4. The noninverting input terminal of the differential amplifier 2 receives a DC voltage V.sub.ref from a constant voltage source 8, with the inverting input terminal thereof receiving a DC voltage V.sub.n from a bleeder network resistance comprising resistors 10 and 12. The differential amplifier 2 compares the voltage from the noninverting input terminal with the voltage from the inverting input terminal to form a differential voltage which in turn is amplified and outputted by the differential amplifier 2. The output transistor 4 has an emitter connected to a power line 15. Thus, the output transistor 4 will receive a power voltage Vcc through a power terminal 14 and the power line 15. The collector of the output transistor 4 is grounded through the resistors 10 and 12.
The resistors 10 and 12 define a bleeder network resistance for feeding the collector current of the output transistor 4 back to the differential amplifier 2 in the form of voltage. More particularly, when the collector current of the output transistor 4 flows in the resistors 10 and 12, a DC voltage is produced between the opposite ends of the series connection of the resistors 10 and 12 (current/voltage conversion). This DC voltage is divided by a particular ratio of resistance therebetween to produce the DC voltage V.sub.n (voltage division). Since the value of the DC voltage corresponds to the value of the collector current, the output voltage of the differential amplifier 2 will correspond to a difference between the value of the collector current and a predetermined value when the DC voltage V.sub.n is applied to the inverting input terminal of the differential amplifier 2 through a feedback line 16 (feedback control of the differential amplifier 2).
The output end of the differential amplifier 2 is connected to the base of the output transistor 4. Therefore, the current taken from the base of the output transistor 4 to the output end of the differential amplifier 2, that is, the value of the base current of the output transistor 4 will be determined depending on the output voltage of the differential amplifier 2. The collector current of the transistor 4 will be determinded by the base current thereof. A voltage V.sub.0 at the collector of the output transistor 4 can be taken from the output terminal 18 as a stabilized output since the collector current of the output transistor 4 is fed back to the differential amplifier 2 in the form of voltage feedback manner, as described.
The stabilizing circuit 6 may be formed as a semiconductor integrated circuit. FIG. 6 shows an example of the output transistor 4 which is formed on a P substrate 20.
The output transistor 4 comprises an N base domain 24, a P.sup.+ emitter domain 30 and a P.sup.+ collector domain 32. The output transistor 4 is surrounded by an isolation domain 26 for separating the output transistor 4 from the other circuit components. The isolation domain 26 may be a P.sup.+ domain formed, for example, by the epitaxial growth or the like. An N.sup.+ implanted layer 22 is formed below the N domain 24 such as by the ion implantation. An N.sup.+ domain 28 is a base contact domain.
When the power voltage V.sub.cc approaches the stabilized output V.sub.0 in the stabilizing circuit 6 as shown in FIG. 5, the output transistor 4 transfers to its saturated state. If the power voltage V.sub.cc is supplied to the system from a battery, a state where the power voltage V.sub.cc approaches the stabilized output V.sub.0, that is, a power reduction state is created on discharge of the battery. The power reduction state is also produced by rapid change in the external load. As the output transistor 4 transfers to its saturated state, a saturation current flows therein. This renders the provision of a preferred stabilized output V.sub.0 difficult.
The fact that the power voltage V.sub.cc approaches the stabilized output V.sub.0 means that in the arrangement of FIG. 6, the difference between the potentials of the emitter and collector domains 30, 32 decreases. If it is now assumed that a parasitic transistor 34 is used, having the P.sup.+ domain 30 as an emitter, the N domain 24 as a base and the isolation domain 26 as a collector, this transistor 34 will be turned on when the potential of the P.sup.+ domain 30 approaches that of the P.sup.+ domain 32 to decrease the difference therebetween. The collector current of the parasitic transistor 34, that is, the rush current that flows from the P.sup.+ domain 30 to the isolation domain 26 and thus toward the substrate 20, is determined depending on the scale of the P.sup.+ domain 30. The P.sup.+ domain 30 defines the emitter domain of the output transistor 4. Thus, the scale of the P.sup.+ domain 30 (i.e. the cross-sectional domain perpendicular to the direction of current in the emitter domain 30) is designed depending on the output current required in the output transistor 4. Normally, the scale of the P.sup.+ domain is relatively large since the current required in the output transistor 4 is relatively large. This means that the rush current from the parasitic transistor 34 to the substrate 20 is also increased.
When the transistor 4 transfers to its saturated state by the power reduction as described, the substrate 20 is heated by the saturated and rush currents to disturb the stabilized potential of the substrate 20. This impairs the operation of the stabilizing circuit 6.
In order to overcome such a disadvantage, it is preferred to arrange the circuit as shown in FIG. 7. In the arrangement of FIG. 7, a saturation preventing circuit 36 for preventing the stabilizing circuit 6 from transferring to its saturated state is located upstream of the stabilizing circuit 6. The saturation preventing circuit 36 comprises a differential amplifier 38, a transistor 40 and resistors 42, 44 and 46. The noninverting input terminal of the differential amplifier 38 receives the reference voltage V.sub.ref from a source of voltage 48, with the inverting input terminal thereof being adapted to receive the reference voltage V.sub.p from the connection P between resistors 44 and 46. The reference voltage V.sub.p is applied to the noninverting input terminal of the differential amplifier 2 in the stabilized circuit 6 so as to be used as the reference voltage in the stabilized circuit 6.
In the power supply, the resistances R.sub.1 ', R.sub.2 ', R.sub.1 and R.sub.2 of the respective resistors 10, 12, 44 and 46 are selected such that the following relationship is achieved therebetween: EQU R.sub.1 :R.sub.2 =R.sub.1 ':R.sub.2 '.
The resistor 42 functions to saturate the transistor 40 having less influence from the parasitic transistor prior to the saturation of the output transistor 4. As the output transistor 40 transfers to its saturated state, the reference voltage V.sub.p will have a value equal to the voltage V.sub.n -(V.sub.ref .times.R.alpha./R.sub.2) (R.alpha.:the resistance of the resistor 42). In the power reduction state, thus, the transistor 40 transfers to its saturated state prior to the saturation of the output transistor 4. As a result, the output transistor is prevented from being saturated. Further, since the transistor 40 requires only a small output current, the current flowing toward the substrate 20 on saturation of the transistor 40 can be sufficiently reduced, compared with the saturation of the output transistor 4.
On stabilization, the output voltage V.sub.0 taken into the output terminal 18 becomes: EQU V.sub.0 =V.sub.ref .times.(R.sub.1 +R.sub.2)/R.sub.2 ( 1)
In such a power supply, however, the rush current created on transfer of the transistor 40 to its saturated state is varied due to variability in manufacture or the like. Thus, the current consumed in the power supply will vary from one product to another. Fluctuations in the saturation voltage of the transistor 40 are reflected to the output voltage V.sub.0 as the reference voltage V.sub.p. As a result, the stabilization will be impaired.